I’d like to start by talking about the biggest misconception regarding RISC-V. Many of you who have heard about RISC-V likely believe it is an open-source processor … but it is not.
So what is it?
RISC-V is an open specification of an Instruction Set Architecture (ISA). That is, it describes the way in which software talks to an underlying processor – just like the x86 ISA for Intel/AMD processors and the ARMv8 ISA for the latest and greatest ARM processors. Unlike those however, the RISC-V ISA is open so that anyone can build a processor that supports it.
What’s the big deal?
For companies supplying products to customers, lock-in is a wonderful thing. It means that once the vendor has the customer it is very hard for the customer to change to a competitor’s product. The best way to create lock-in is to have good-enough products and a rich ecosystem. That way, once you have the customer, they have invested too much into the implementation and you have them locked-in for a very long time. Any new competitor must have a better product, but also build an equivalent ecosystem. Even then it will be almost impossible for a customer to do apples-to-apples comparison based on the merits of the solution.
Just like the old saying that no one ever got fired for buying IBM, these days it is accepted that no-one ever gets fired for using ARM processors. There is a dark side to this however. If companies are not able to compete on the merit of their solutions, progress stagnates. Companies invest just enough to keep customers happy – no more, no less.
RISC-V changes this dynamic since a single software ecosystem built on the RISC-V standard supports many different processor vendors, and the processor vendors must now compete on the merit of their product for different applications. Customers don’t need to settle for good-enough, and competition will mean a significant acceleration of innovation in embedded processors. Also, without the need for each new processor startup to build an expensive ecosystem, many new innovative processor companies will appear.
What’s the downside?
For customers there is none. For processor IP companies, good-enough is no longer enough. Vendors like Codasip will have to ensure we are meeting and exceeding the customer’s needs and supplying the best possible solution, or they can easily move to a new supplier. Some analysts believe RISC-V will lead to commoditization of the processor IP, however, I believe it will lead to specialization and innovation. It will not be a race to the bottom, but rather an opportunity to supply additional value to customers and users.
How does Open-Source fit into this?
Thanks to the work of a number of academic institutions – especially UC-Berkley, the original creators of the RISC-V specification – there are a number of free open-source implementations of the RISC-V ISA. These open source implementations are already allowing various academic and open source SoC projects to do work that would have been impossible without an open standard. More importantly, however, commercial companies are free to create their own implementation of RISC-V processors. This gives customers an even greater range of options.
How does RISC-V fit with Codasip and application optimized processors?
RISC-V is a layered and extensible ISA which means a processor can implement the minimal instruction set, well defined extensions, and custom extensions for a given application. As long as the minimal set needed for a given application is implemented, that application will run on any compatible processor.
This removes one of the biggest barriers for application optimized processors, the effort required to develop the ancillary software around the processor. As such, up until now, most ASIPs (Application Specific Instruction-set Processors) have been used in deeply embedded environment where the software environment was limited, and well defined. Having a common software ecosystem means customers will now be free to add application extensions to any processor, being able to take advantage of the significant improvements they provide, without the downside.
Who maintains the standard?
The standard is maintained by the RISC-V foundation (riscv.org), with foundation members (including Codasip) coming from across the industry including software, systems, semiconductor and IP. The focus of member companies is on building a rich ecosystem of hardware and software that will rival or surpass that of companies like ARM.
So what happens next?
Unfortunately I don’t have a magic crystal ball, but after many years in the semiconductor industry, what I can say is that I have never before seen so much interest in a new standard, and such a diverse set of companies working together to make it a reality – including processor IP competitors all targeting the same specification.
I expect that we will see an explosion of innovation and growth, very similar to what happened in the enterprise software space once people were able to build on common open standards.
About the RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. The Foundation has a Board of Directors comprising seven representatives from Bluespec, Inc.; Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.
Each year, the RISC-V Foundation hosts global events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the instruction set architecture (ISA) forward. Event sessions feature leading technology companies and research institutions discussing the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. Learn more by visiting the Event Proceedings page.