he RISC-V authors aim to provide several CPU designs freely available under BSD licenses, which allow derivative works, such as RISC-V chip designs, to be either open and free, as is RISC-V, or closed and proprietary.
By contrast, commercial chip vendors such as ARM Holdings and MIPS Technologies charge substantial license fees for the use of their patents. They also require non-disclosure agreements before releasing documents that describe their designs’ advantages and instruction set. This secrecy makes security auditing significantly more difficult.
Developing a CPU requires design expertise in several specialties: electronic digital logic, compilers, and operating systems. It is rare to find this outside of a professional engineering team. The result is that modern, high-quality general-purpose computer instruction sets have not recently been widely available anywhere, or even explained, except in academic settings. Because of this, many RISC-V contributors see it as a unified community effort. This need for a large base of contributors is part of the reason why RISC-V was engineered to fit so many uses.
The RISC-V authors also have substantial research and user-experience validating their designs in silicon and simulation. The RISC-V ISA is a direct development from a series of academic computer-design projects. It was originated in part to aid such projects.